The present invention relates to a general-purpose computer system having no vector register. More particularly, the invention concerns a computer system best suited for speeding up list processings or operations. ations.
A typical arrangement of the general-purpose computer to which the present invention is directed is schematically shown in FIG. 4 of the accompanying drawings. Referring to this figure, an instruction control unit 1 is destined for decoding instructions to be performed in the computer system, issuing operation commands to an arithmetic operation unit 2 and a memory control unit 3, controlling the sequence in which the instructions are executed, and so forth. The memory control unit 3 performs reading of data (also referred to as data fetch or fetching) from a main memory 4 and writing of data (also referred to as data store or storing) in the main memory 4. The latter is composed of a storing medium assigned with addresses. The data fetching as well as data storing operation to the main memory 4 is under command of the memory control unit 3. In the following description, the term "address" refers to the main memory 4 unless otherwise specified. A group of general-purpose registers generally denoted by a numeral 5 comprises a plurality of registers imparted with respective identification numbers. The number of the register to be used is designated by the instruction.
Now, it is assumed that a vector operation is to be performed with the general-purpose computer system shown in FIG. 4. In such case, an integrated array processor (referred to IAP in abbreviation) is usually added to the operation unit 2 for performing the vector processing or operation at a high speed. For particulars of the IAP, reference may be made, for example, to "Manual of HITAC M-180/200 H/280 H Integrated Array Processor" (Data Number 8080-2-041-20). In this conjunction, the instruction which requires the use of the IAP for its execution is referred to as an IAP instruction (or vector instruction).
A format of the IAP instruction is shown in FIG. 5. Operation of the instruction is designated by the "value of the general-purpose register indicated in the field B plus the value of the field D". The general-purpose register indicated in a field R1 stores therein an initial count indicative of the origin of a vector element to be processed. A general-purpose register indicated in a field (R1+1) stores therein a vector length which corresponds to the number of times the operation or processing is to be performed. The general-purpose register indicated in a field R3 designates the main memory address for the first byte of an operand address vector (referred to as OAV in abbreviation). The OAV is a table on the main memory which designates the address of a vector descriptor table (abbreviated to VDT) for the vector operand. More specifically, the OAV includes a leading address of VDT 2 (i.e. VDT of the second operand), a leading address of VDT 3 (i.e. VDT of the third operand), a leading address of VDT 1 (i.e. VDT of the first operand), and address of a control vector, as can be seen in FIG. 5.
The VDT has a format illustrated in FIG. 6. As will be seen, the VDT includes the address of the vector element at the leftmost or rightmost end (i.e. the address of the vector element to be first processed), a flag and an increment value (interval or space between vector elements).
The control vector consists of a bit string of "0s" or "1s+ and is formatted in a manner illustrated in FIG. 7. Individual bits of the control vector correspond to the operation units. More specifically, the leftmost bit as viewed in FIG. 7 corresponds to the initial count "0", the second leftmost bit corresponds to the count "1", the third leftmost bit to "2", and so forth. The length (n) of the control vector corresponds to the number indicated by the general-purpose register which in turn is designated by "the number in the field R1 plus 1".
The IAP instruction commands the operation on the second and third operands, the result of which is written in the first operand. The type of operation or processing is designated by "value of the general-purpose register indicated in the field B plus the value of the field D" mentioned hereinbefore, while the address of each operand vector is given by the aforementioned VDT. The position of the operand first to be processed is determined by an algebraic sum of the leading address of each operand and the product of the initial count indicated by the aforementioned field R1 and the increment value contained in the VDT. The content of the general-purpose register indicated by the field R1 is incremented by one every time an operation for a set of vector elements has been completed, wherein the next operation is performed on the operand located at the address corresponding to an algebraic sum of the leading address of each operand and the product of the number in the register or field R1 and the increment value contained in VDT. When the content of the register R1 becomes equal to that of the register (R1+1), execution of the instruction comes to an end. It should be mentioned that the control vector serves for enabling execution of the operation.
Nw, let's consider a program which is expressed by FORTRAN sentences as follows: EQU DO 10 I=1, 100 EQU A(I)=B[C(I)] EQU 10 CONTINUE
This program represents an operation on an array of arguments of other arrays, i.e. a so-called list operation or processing in which the element numbers of a vector constitute elements of another vector.
In this connection, it is noted that the hitherto known general-purpose computer system additionally provided with the IAP is not so arranged as to support the list operation. Accordingly, in order to execute the above list operation, the elements must be processed one by one (i.e. the vector elements must be processed one by one with the aid of a load instruction, store instruction and others), requiring a lot of time.